This application relies for priority upon Korean Patent Application No. 2002-7695, filed on Feb. 9, 2002, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to method of fabricating a semiconductor device and, more specifically, to a dynamic random access memory (DRAM) device having a fuse.
A DRAM device comprises a cell array area and a peripheral circuit area. The cell array area includes a plurality of unit cells, each of which comprises a MOS transistor and a storage capacitor. The peripheral circuit area consists of semiconductor circuits that control operations and input/output of the unit cells, for example a driver, a buffer or an amplifier. The peripheral circuit area usually includes a plurality of fuses, which can be cut by using a laser.
In continuing the trend of higher memory capacity, three-dimensional capacitors have been proposed in an attempt to increase an effective capacitor area in the unit cell. The three-dimensional capacitors have, for example, concave type or cylinder type storage electrodes. The heights of the three-dimensional capacitors are relatively high, as much as 1 xcexcm or more, to retain a desirable cell capacitance of the unit cell and solve problems such as low read-out capability of the cell and low immunity to soft error. However, the heights of the three-dimensional capacitors may induce a high global step difference between the cell array area and the peripheral circuit area. The global step difference may make it difficult to form a metal interconnection, which is usually formed after the formation of the capacitors.
One proposal to reduce the global step difference is to form a thick interlayer insulating layer on the global step difference and make the surface of the interlayer insulating layer planar. FIGS. 1a through 1c are cross-sectional views illustrating successive process steps for forming a fuse opening according to a conventional method. Referring to FIG. 1a, isolation regions 11 are formed on a semiconductor wafer 10, thereby defining active regions. MOS transistors 15 are formed on the semiconductor wafer 10 having the isolation regions 11. Each of the MOS transistors 15 comprises a gate electrode 12, a source 14a and a drain 14b. The sources 14a and the drains 14b are formed in the active regions of the semiconductor wafer 10. The MOS transistors 15 in a cell array area are formed more densely than the MOS transistors 15 in a peripheral circuit area. Each of the gate electrodes 12 comprises a gate dielectric layer 19 formed on the active regions of the semiconductor wafer 10, a gate conductive layer 21 formed on the gate dielectric layer 19, a hard mask layer 25 formed on the gate conductive layer 21 and spacers 27 formed on the sidewalls of the gate conductive layers 21. Between the gate electrodes 12, SAC (self-aligned contact) pads 16 are formed to contact the sources 14a and the drains 14b. 
On the resultant structure, a first interlayer insulating layer 18 is formed. On the first interlayer insulating layer 18, bit lines (though not shown) and fuse 20 are formed in the cell array area and in the peripheral circuit area, respectively. The bit lines are electrically connected to the drains 14b. Though not shown, during formation of the bit line and fuse 20, a local interconnection may be formed simultaneously on the first interlayer insulating layer 18 in the peripheral circuit area.
On the resultant structure, a second interlayer insulating layer 22 is formed. Subsequently, storage contact holes are formed through the first and second interlayer insulating layers 18, 22. The storage contact holes expose the SAC pads 16, which are formed on the sources 14a. Conductive storage contact pads 23 are formed to fill the storage contact holes.
Storage capacitors 30 are formed on the resultant structure. Each of the storage capacitors 30 comprises a concave type storage electrode 24, a capacitor dielectric layer 26 formed on the storage electrode 24 and a plate electrode 28 formed on the capacitor dielectric layer 26. The concave type storage electrodes 24 are formed to electrically contact to the storage contact pads 23. The storage electrodes 24 are formed only in the cell array area, while the plate electrode 28 is formed in both the cell array area and the peripheral circuit area. As a result, as shown in the drawing, a first global step difference X1 is generated. Though not shown, the plate electrode 28 may be formed only in the cell array area. In this case, the first global step difference XI may be greater compared to that in case of that the plate electrode 28 is formed both in the cell array area and in the peripheral circuit area.
A third interlayer insulating layer 32 is formed on the plate electrode 28. The third interlayer insulating layer 32 is thick enough to bury the first global step difference X1. That is to say, the thickness of the third interlayer insulating layer 32 is greater than the first global step difference X1. The third interlayer insulating layer 32 may be formed by a method to make the top surface of the resultant structure planarized to some extent, so that a second global step difference X1xe2x80x2 of the resultant structure can be smaller than the first global step difference X1. However, it is very difficult to completely remove the second global step difference X1xe2x80x2.
Referring to FIG. 1b, a top portion of the third interlayer insulating layer 32, which is located over the storage electrodes 24, is removed to reduce the global step difference between the cell array area and the peripheral circuit area. This process is well known in the industry as a cell open process. As a result of the cell open process, a protrusion 34 of the third interlayer insulating layer 32 remains. Preferably, the altitude level of the top surface of the third interlayer insulating layer 32 in the cell array area is adjusted by the cell open process to be substantially the same as that in the peripheral area, thereby substantially removing the global step difference.
Referring to FIG. 1c, the third interlayer insulating layer 32 is subject to a CMP (chemical mechanical polishing) process to remove the protrusion 34 and make the whole surface of the third interlayer insulating layer 32 more perfectly planarized, thereby leaving a planarized interlayer insulating layer 32a. 
Though not shown in the drawings, on the planarized interlayer insulating layer 32a, a multilevel metal interconnection including an intermetal insulating layer is formed. A passivation layer (though not shown) is formed on the multilevel metal interconnection. Subsequently, the passivation layer, the intermetal insulating layer, the planarized interlayer insulating layer 32a, the plate electrode 28 and the second interlayer insulating layer 22 are selectively etched to form a fuse opening on the fuse 20, though not shown in the drawings. The reference number xe2x80x9835xe2x80x99 represents a portion of the planarized interlayer insulating layer 32a, which is to be removed to form the fuse opening.
One problem in the above-described method for forming the fuse opening is that the thickness of the planarized interlayer insulating layer 32a is too thick in the peripheral circuit area as a result of the process for reducing the global step difference and removing the protrusion 34. Therefore, the depth of the portion 35 of the planarized insulating layer 32a to be etched is too large, resulting in an unfavorably long etching time. The large etching amount and the long etching time may result in low productivity.
Accordingly, the need remains for a method for forming DRAM devices to reduce the etching amount and time for forming a fuse opening, while at the same time significantly reducing the substantial global step difference between a cell array area and a peripheral circuit area.
It is an object of the present invention to provide a method for forming a semiconductor device with high productivity.
It is another object of the present invention to provide a method for forming a semiconductor device having a fuse, wherein the etching amount for forming a fuse opening is low.
It is another object of the present invention to provide a method for forming a semiconductor device having a fuse, wherein the etching time for forming a fuse opening is low, and wherein the global step difference between a cell array area and a peripheral circuit area is significantly reduced.
According to one aspect of the present invention, a method of fabricating a semiconductor device is provided. The method comprises providing a substrate including a first area, a second area and a global step difference between the first and the second areas. The substrate comprises a fuse formed in the second area of the substrate. An interlayer insulating layer is formed on the substrate. A first portion of the interlayer insulating layer in the first area and a second portion of the interlayer insulating layer in the second area are removed simultaneously, thereby decreasing the global step difference and defining a first recess in the interlayer insulating layer in the second area. The first recess is defined over the fuse. The interlayer insulating layer is planarized after defining the first recess. A metal pattern is formed on the interlayer insulating layer. An intermetal insulating layer is formed on the metal pattern. A first portion of the intermetal insulating layer is removed to expose a portion of the metal pattern, thereby forming a via hole through the intermetal insulating layer. Simultaneously, a second portion of the intermetal insulating layer in the second area and a third portion of the interlayer insulating layer in the second area are removed, thereby defining a second recess in a composite layer of the interlayer insulating layer and the intermetal insulating layer in the second area. The second recess is defined over the fuse. A passivation layer is formed on the interlayer insulating layer. A fuse opening is formed on the fuse. The fuse opening is formed through the passivation layer, the interlayer insulating layer, the first recess and the second recess. The first area is a cell array area and the second area is a peripheral circuit area. The width of the first recess is greater than that of the fuse opening. The width of the second recess is greater than that of the fuse opening. The width of the first recess is greater than that of the second recess.
According to another aspect of the present invention, a method of fabricating a semiconductor device is provided. The method comprises providing a substrate including a first area, a second area and a global step difference between the first area and the second area. The substrate comprises a fuse formed in the second area and a conductive layer. The conductive layer is formed in the first and second areas. The conductive layer is formed over the fuse. An interlayer insulating layer is formed on the substrate. A fourth portion of the interlayer insulating layer is removed to form a contact hole. A fifth portion of the interlayer insulating layer is removed to define a first recess in the interlayer insulating layer in the second area. The fourth and fifth portions of the interlayer insulating layer are removed simultaneously. The contact hole exposes a first portion of the conductive layer. The first recess exposes a second portion of the conductive layer in the second area. The first portion of the conductive layer is in the second area. The first recess is defined over the fuse. A conductive plug is formed in the contact hole. A metal pattern is formed on the interlayer. insulating layer. The metal pattern is electrically connected to the conductive plug. An intermetal insulating layer is formed on the metal pattern. A first portion of the intermetal insulating layer is removed to expose a portion of the metal pattern, thereby forming a via hole through the intermetal insulating layer. Simultaneously, a second portion of the intermetal insulating layer in the second area is removed, thereby defining a second recess in the intermetal insulating layer in the second area. The second recess is defined over the fuse and exposes a third portion of the conductive layer. A passivation layer is formed on the interlayer insulating layer. A fuse opening is formed on the fuse. The fuse opening is formed through the passivation layer, the conductive layer and the first recess. The second recess is defined within the first recess. The width of the first recess is greater than that of the fuse opening. The width of the second recess is greater than that of the fuse opening. The width of the first recess is greater than that of the second recess.
According to another aspect of the present invention, a method of fabricating a semiconductor device is provided. The method comprises providing a substrate including a first area, a second area and a global step difference between the first area and the second area. The substrate comprises a fuse formed in the second area. An interlayer insulating layer is formed on the substrate. A metal pattern is formed on the interlayer insulating layer. An intermetal insulating layer is formed on the metal pattern. A first portion of the intermetal insulating layer is removed to expose a portion of the metal pattern, thereby forming a via hole through the intermetal insulating layer. Simultaneously, a second portion of the intermetal insulating layer in the second area removed to define a recess. The recess is defined over the fuse. A passivation layer is formed on the interlayer insulating layer. A fuse opening is formed on the fuse. The fuse opening is formed through the passivation layer and the recess. The width of the recess is greater than that of the fuse opening. During the simultaneous removal, a portion of the interlayer insulating layer may be further removed, thereby extending the recess into the interlayer insulating layer in the second area.